1. Field of the Invention
The invention relates to an integrated semiconductor circuit, comprising a divide-by-two frequency divider circuit which comprises a loop which includes an inverter stage A, a follower stage B and a channel of an interrupt transistor which is controlled by a control signal.
The invention is used for the formation of digital integrated gallium arsenide hyperfrequency circuits, notably for frequency-stabilized sources or programmable dividers enabling synthesization of a set of stabilized frequencies.
2. Description of the Prior Art
It is generally known that in comparison with a static circuit a dynamic divide-by-two divider circuit utilises fewer active components and that the propagation time (Tpd) of a gate is shorter.
For comparison in this respect see the divider circuit described in "26GHz GaAs Room-Temperature Dynamic Divider circuit" by J. F. Jensen, L. G. Salmon et al in "GaAs IC Symposium" pp. 201-204, reference CH2506-4/87/0000-0201-C-1987 IEEE, and the circuit described in "Ultrahigh Speed GaAs Static Frequency Dividers" by J. F. Jensen, L. G. Salmon et al in "IEDM 86 pp. 476-479", reference CH 2381-2/86/0000-0476-C-1986 IEEE.
The first of said documents describes a dynamic divide-by-two frequency divider circuit which is based on the use of depletion-type field effect transistors having a pinch-off voltage of approximately -2.5 V. The divider is composed of two stages (see FIG. 5 of the first document).
The first stage is formed by an interrupt transistor which is controlled by the first clock signal .phi. and which is followed by an inverter gate of the BFL (Buffered FET Logic) type (described in FIG. 4 of the second document). The second stage is formed by an interrupt transistor which is controlled by the second, complementary clock signal .phi. and which is followed by a follower gate.
The logic states are stored by charging or discharging the gate capacitances of the inverter and follower transistors.
The speed of the circuit is limited by the propagation time of the two gates (2Tpd).
The known dynamic divider circuit obviously has the advantage that it can be realised by means of a number of transistors which is substantially smaller than that used in the divider circuit described in the second document and that it has a shorter propagation time per gate (Tpd). This results in a lower power consumption, a greater suitability for large scale integration, and a higher maximum operating frequency.
However, even though the circuit described in the first document has a number of advantages, for a technical field where ever more powerful circuits are desired it still has a given number of drawbacks.
The maximum frequency is limited by the two gate propagation times: EQU F.sub.max .perspectiveto.1/(2 Tpd).
On the other hand, this circuit comprises two interrupt transistors each of which is controlled by two complementary clock signals.
The difficulty thus consists in that:
either these two complementary clock signals must be supplied by an external circuit,
or they must be generated in the circuit itself.
In the one as well as in the other case the problem exists that it is necessary to generate two strictly complementary clock signals having high frequencies such as those in the field envisaged by the present invention, that is to say approximately 20 Ghz.